BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20181221T160728Z
LOCATION:D172
DTSTART;TZID=America/Chicago:20181112T141000
DTEND;TZID=America/Chicago:20181112T150000
UID:submissions.supercomputing.org_SC18_sess168_pec331@linklings.com
SUMMARY:Versal: The New Xilinx Adaptive Compute Acceleration Platforms (AC
 AP)
DESCRIPTION:Workshop\nArchitectures, Data Analytics, Graph Algorithms, Wor
 kshop Reg Pass\n\nVersal: The New Xilinx Adaptive Compute Acceleration Pla
 tforms (ACAP)\n\nVissers\n\nIn this presentation, I will present the new A
 daptive Compute Acceleration Platform. I will show the overall system arch
 itecture of the family of devices including the Arm cores (scalar engines)
 , the programmable logic (Adaptable Engines) and the new vector processor 
 cores (AI engines). I will focus on the new AI engines in more detail and 
 show the concepts for the programming environment, the architecture, the i
 ntegration in the total device, and some application domains, including Ma
 chine Learning and 5G wireless applications. I will illustrate the initial
  design rationale and the architecture trade-offs. These platforms extend 
 the concept of tuning the memory hierarchy to the problem.
URL:https://sc18.supercomputing.org/presentation/?id=pec331&sess=sess168
END:VEVENT
END:VCALENDAR