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DTSTAMP:20181221T160725Z
LOCATION:D167/174
DTSTART;TZID=America/Chicago:20181111T103000
DTEND;TZID=America/Chicago:20181111T104500
UID:submissions.supercomputing.org_SC18_sess170_ws_h2rc115@linklings.com
SUMMARY:SimBSP: Enabling RTL Simulation for Intel FPGA OpenCL Kernels
DESCRIPTION:Workshop\nAccelerators, Heterogeneous Systems, NVRAM, Workshop
  Reg Pass\n\nSimBSP: Enabling RTL Simulation for Intel FPGA OpenCL Kernels
 \n\nHerbordt, Sanaullah\n\nRTL simulation is an integral step in FPGA deve
 lopment since it provides cycle accurate information regarding the behavio
 r and performance of custom architectures, without having to compile the d
 esign to actual hardware. Despite its advantages, however, RTL simulation 
 is not currently supported by a number of commercial FPGA OpenCL toolflows
 , including Intel OpenCL SDK for FPGAs (IOCLF). Obtaining reliable perform
 ance values for OpenCL kernels requires a full compilation to hardware, wh
 ile emulation can only provide functional verification of the C code. Thus
 , development and optimization time-frames for IOCLF designs can be on the
  order of days, even for simple applications. In this work, we present our
  custom Board Support Package for IOCLF, called SimBSP, which enables Open
 CL kernels to be compiled for RTL simulation. \n\nWe provide details regar
 ding the standard kernel ports created by the IOCLF compiler, which can be
  used by testbenches to interface the generated design. We also list the a
 ddresses and descriptions of configuration registers that are used to set 
 kernel parameters and provide a start trigger. Finally, we present details
  of SimBSP toolflow, which is integrated into the standard IOCLF and autom
 ates the process of generating kernel HDL and testbenches, and setting up 
 the simulation environment. Our work on SimBSP will be made available Open
  Source to drive a community effort towards further improving the toolflow
 .
URL:https://sc18.supercomputing.org/presentation/?id=ws_h2rc115&sess=sess1
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