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DTSTAMP:20181221T160729Z
LOCATION:C141/143/149
DTSTART;TZID=America/Chicago:20181113T110000
DTEND;TZID=America/Chicago:20181113T113000
UID:submissions.supercomputing.org_SC18_sess203_pap109@linklings.com
SUMMARY:FlipTracker: Understanding Natural Error Resilience in HPC Applica
 tions
DESCRIPTION:Paper\nGPUs, Resiliency, State of the Practice, System Softwar
 e, Tech Program Reg Pass\n\nFlipTracker: Understanding Natural Error Resil
 ience in HPC Applications\n\nGuo, Li, Laguna, Schulz\n\nAs high-performanc
 e computing systems scale in size and computational power, the danger of s
 ilent errors, i.e., errors that can bypass hardware detection mechanisms a
 nd impact application state, grows dramatically. Consequently, application
 s running on HPC systems need to exhibit resilience to such errors. Previo
 us work has found that, for certain codes, this resilience can come for fr
 ee, i.e., some applications are naturally resilient, but few works have sh
 own the code patterns—combinations or sequences of computations—that make 
 an application naturally resilient. In this paper, we present FlipTracker,
  a framework designed to extract these patterns using fine-grained trackin
 g of error propagation and resilience properties, and we use it to present
  a set of computation patterns that are responsible for making representat
 ive HPC applications naturally resilient to errors. This not only enables 
 a deeper understanding of resilience properties of these codes, but also c
 an guide future application designs toward patterns with natural resilienc
 e.
URL:https://sc18.supercomputing.org/presentation/?id=pap109&sess=sess203
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