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DTSTAMP:20181221T160731Z
LOCATION:C141/143/149
DTSTART;TZID=America/Chicago:20181114T153000
DTEND;TZID=America/Chicago:20181114T160000
UID:submissions.supercomputing.org_SC18_sess215_pap431@linklings.com
SUMMARY:Associative Instruction Reordering to Alleviate Register Pressure
DESCRIPTION:Paper\nAlgorithms, Applications, Architectures, Compiler Analy
 sis and Optimization, Floating Point, Performance, Precision, Programming 
 Systems, Tools, Tech Program Reg Pass\n\nAssociative Instruction Reorderin
 g to Alleviate Register Pressure\n\nRawat, Sukumaran-Rajam, Rountev, Raste
 llo, Pouchet...\n\nRegister allocation is generally considered a practical
 ly solved problem. For most applications, the register allocation strategi
 es in production compilers are very effective in controlling the number of
  loads/stores and register spills. However, existing register allocation s
 trategies are not effective and result in excessive register spilling for 
 computation patterns with a high degree of many-to-many data reuse, e.g., 
 high-order stencils and tensor contractions.  We develop a source-to-sourc
 e instruction reordering strategy that exploits the flexibility of reorder
 ing associative operations to alleviate register pressure.  The developed 
 transformation module implements an adaptable strategy that can appropriat
 ely control the degree of instruction-level parallelism, while relieving r
 egister pressure.  The effectiveness of the approach is demonstrated throu
 gh experimental results using multiple production compilers (GCC, Clang/LL
 VM) and target platforms (Intel Xeon Phi, and Intel x86 multi-core).
URL:https://sc18.supercomputing.org/presentation/?id=pap431&sess=sess215
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