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DTSTART:19700308T020000
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DTSTAMP:20181221T160731Z
LOCATION:C146
DTSTART;TZID=America/Chicago:20181114T143000
DTEND;TZID=America/Chicago:20181114T150000
UID:submissions.supercomputing.org_SC18_sess216_pap386@linklings.com
SUMMARY:Evaluating and Accelerating High-Fidelity Error Injection for HPC
DESCRIPTION:Paper\nPerformance, Resiliency, Tools, Tech Program Reg Pass\n
 \nEvaluating and Accelerating High-Fidelity Error Injection for HPC\n\nCha
 ng, Lym, Kelly, Sullivan, Erez\n\nWe address two important concerns in the
  analysis of the behavior of applications in the presence of hardware erro
 rs: (1) when is it important to model how hardware faults lead to erroneou
 s values (instruction-level errors) with high fidelity, as opposed to usin
 g simple bit-flipping models, and (2) how to enable fast high-fidelity err
 or injection campaigns, in particular when error detectors are employed. W
 e present and verify a new nested Monte Carlo methodology for evaluating h
 igh-fidelity gate-level fault models and error-detector coverage, which is
  orders of magnitude faster than current approaches. We use that methodolo
 gy to demonstrate that, without detectors, simple error models suffice for
  evaluating errors in 9 HPC benchmarks.
URL:https://sc18.supercomputing.org/presentation/?id=pap386&sess=sess216
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