BEGIN:VCALENDAR
VERSION:2.0
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BEGIN:VTIMEZONE
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X-LIC-LOCATION:America/Chicago
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RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
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BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
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DTSTAMP:20181221T160731Z
LOCATION:D171
DTSTART;TZID=America/Chicago:20181114T113000
DTEND;TZID=America/Chicago:20181114T120000
UID:submissions.supercomputing.org_SC18_sess271_exforum139@linklings.com
SUMMARY:Accelerate Machine Learning with High Performance Memory
DESCRIPTION:Exhibitor Forum\nMachine Learning\n\nAccelerate Machine Learni
 ng with High Performance Memory\n\nHur\n\nMachine learning is driving the 
 next industrial revolution, through the use of easy to program accelerator
  boards, you can be in the driver seat. In this talk, Micron will discuss 
 a new novel inference engine architecture that provides the benefits of ha
 rdware acceleration, that supports a wide range of ML frameworks and netwo
 rks; and is software programmable.  This new architecture/platform is a fl
 exible and programmable neural network accelerator co-processor is designe
 d for 1) maximum hardware utilization, 2) efficient memory bandwidth usage
 , 3) ultra-low power operation.  This architecture coupled with a ML compl
 ier allows the user to take advantage of hardware acceleration while maint
 aining software programmability.
URL:https://sc18.supercomputing.org/presentation/?id=exforum139&sess=sess2
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