BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20181221T160910Z
LOCATION:Exhibit Hall B
DTSTART;TZID=America/Chicago:20181114T091500
DTEND;TZID=America/Chicago:20181114T100000
UID:submissions.supercomputing.org_SC18_sess507_pec441@linklings.com
SUMMARY:Kennedy Award Presentation - Memory Consistency Models: They Are B
 roken and Why We Should Care
DESCRIPTION:Awards Presentation\nTech Program Reg Pass, Exhibits Reg Pass\
 n\nKennedy Award Presentation - Memory Consistency Models: They Are Broken
  and Why We Should Care\n\nAdve\n\nThe memory consistency model for a shar
 ed address space specifies the value a load can return, affecting programm
 ability and performance. For such a fundamental property, it, unfortunatel
 y, still routinely causes heads to spin.  I will first briefly trace the e
 volution of memory models over three decades. The 1990s saw an explosion i
 n memory models from hardware vendors and researchers. The 2000s drove a c
 onvergence centered on the more software-centric view of the data-race-fre
 e model. The last decade has struggled with mind-twisting implications of 
 “out-of-thin-air” values and relaxed atomics, pointing to a fundamentally 
 broken paradigm for hardware and software.\n\nThe end of Moore’s law is dr
 iving transformational change in hardware with specialization and heteroge
 neity within and across chips, including application-specialized and heter
 ogeneous parallelism, coherence, and communication. How does this affect t
 he memory model, or more broadly, the hardware-software interface? From ou
 r recent research in the DeNovo project, I will show examples of how we ar
 e again in danger of repeating the mistakes of the hardware-centric 1990s 
 to create another memory model mess. On the other hand, there is a golden 
 opportunity for hardware-software cooperation to redefine our interface fr
 om the ground up and find a fundamental resolution to the problem. I belie
 ve this will require rethinking how we represent parallelism, communicatio
 n, and correctness in software, how we provide coherence and communication
  in hardware, and that the HPC community’s expertise in how to explicitly 
 manage communication will have a key role to play.
URL:https://sc18.supercomputing.org/presentation/?id=pec441&sess=sess507
END:VEVENT
END:VCALENDAR