Presenter

Johannes is a PhD student at the Scalable Parallel Computing Group at ETH Zurich under the supervision of Prof. Torsten Hoefler, where he conducts research in the area of high-performance computing on reconfigurable hardware. With more than two years experience with high-level synthesis tools from both Intel and Xilinx, Johannes has accumulated a deep understanding of their features and quirks, in particular in the context of massively parallel designs targeting HPC applications. He interned with Xilinx Ireland, where he devised and demonstrated techniques to reach peak performance on large FPGA chips, including for problems that are traditionally memory bound on CPU and GPU. In addition to applying and teaching these techniques, Johannes is interested in new abstractions and programming models to guide and/or automate the development of FPGA programs for HPC, as well as new hardware architectures